Re: sparc64 cmpxchg is not a full memory barrier anymore ?

[David Miller]

From: Mathieu Desnoyers <mathieu.desnoyers@xxxxxxxxxx>
Date: Thu, 22 Oct 2009 14:32:42 -0400

> The same applies to the other atomic instructions we find in this list.
> How is the correct ordering of loads wrt to cmxchg (and other atomic
> ops) still ensured by this modification?

All actual sparc64 chips implement more strict ordering than
the V9 specification permits.  The memory barriers were just
nops and actually not doing anything more than the chip
already does for us.
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