Patch adds DT entries for clockgen A0Note that I removed this comment since no SASG2 on STiH407.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@xxxxxxxxxx>
Signed-off-by: Olivier Bideau <olivier.bideau@xxxxxx>
---
arch/arm/boot/dts/stih407-clock.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 800f46f..e03e86e 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -7,6 +7,10 @@
*/
/ {
clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
/*
* Fixed 30MHz oscillator inputs to SoC
*/
@@ -35,5 +39,33 @@
clock-frequency = <200000000>;
clock-output-names = "clk-s-icn-reg-0";
};
+
+ /*
+ * ClockGenAs on SASG2
+ */
+ clockgen-a@090ff000 {...
+ compatible = "st,clkgen-c32";
+ reg = <0x90ff000 0x1000>;