Re: [PATCH V5 11/18] clk: tegra210: Add support for Tegra210 clocks

[Sowjanya Komatineni]

On 7/18/19 10:41 AM, Sowjanya Komatineni wrote:
> On 7/18/19 10:22 AM, Sowjanya Komatineni wrote:
> > On 7/18/19 9:34 AM, Dmitry Osipenko wrote:
> > > 18.07.2019 4:15, Sowjanya Komatineni ÐÐÑÐÑ:
> > >
> > > [snip]
> > >
> > > > > > Please try to fix all missing dependencies and orderings.
> > > > > Peter,
> > > > >
> > > > > dfllCPU_OUT is the first one to go thru restore when
> > > > > clk_restore_context traverses thru the list.
> > > > >
> > > > > dfllCPU_OUT has dependency on DFLL_ref and DFLL_SOC but this
> > > > > dependency is unknown to clock-tree.
> > > > >
> > > > > We can add DFLL_REF and DFLL_SOC as parents to dfllCPU_OUT during
> > > > > register so dfllCPU_OUT save/restore happens after their parents are
> > > > > restored.
> > > > >
> > > > > But DFLL needs both of these to be restored before DFLLCPU_Out and as
> > > > > DFLL_SOC restore always happens after the REF, thinking to add
> > > > > DFLL_SOC as parent to dfllCPU_OUT so save/restore follows after their
> > > > > dependencies.
> > > > >
> > > > > Please comment.
> > > > Did quick try and I see by adding dfll-soc as parent to 
> > > > dfllCPU_OUT, its
> > > > in proper order after all its dependencies.
> > > >
> > > > Can now add dfll save/restore to do dfll reinit during restore..
> > > If dfllCPU_OUT can work properly with dfll-soc being disabled, then 
> > > this
> > > kind of dependency isn't very correct and just papers over the real
> > > problem, which is that there should be a way for CCF to specify 
> > > multiple
> > > dependencies for the clock or the reverse ordering should be used for
> > > the restoring.
> >
> > dfll will not work without dfll-soc enabled.
> >
> > CLDVFS control logic is split into 2 clock domains. dvfs_ref_clk and 
> > dvfs_soc_clk.
> >
> > Majority of the control logic is clocked from dvfs_soc_clk for 
> > interfacing control registers.
> Note on reverse ordering for restore. Currently restore order goes 
> thru clock list and for each root goes thru parent -> child restore.
>
> this order is correct and also all clocks are parented properly so 
> they follow proper order.
>
> dfllCPU is the only one where current driver doesn't take care of 
> dependency in dfll_soc which gets enabled only after dfll_ref.
>
>
> Based on dfllCPU control logic module design, dfll_ref and dfll_soc 
> should be enabled prior to dfll init/enable.
>
> So parenting dfll_soc to dfllCPU keeps proper order.

1. With dfllCPU parenting to dfll_soc, its keeps it in expected order 
and we don't define any parent clk_ops anyway for this, so should be OK?

OR

2. Any suggestion on how to define/specify dependencies for clock other 
than parenting to follow proper order in clock tree as clk_save_context 
and clk_restore_context strictly goes thru clock tree order and all 
other clocks are parented properly except for dfllCPU where there is no 
parent. Techinically dfll_ref & dfll_soc are not parents but they need 
to be configured prior to dfll reinit.

OR

3. I don't see way to override clk_save_context/clk_restore_context APIs 
to change the way of traversal so I can modify to traverse in expected 
order without dfllCPU parenting.

OR

4. dfll re-init can be done in dfll-fcpu driver pm_ops which actually 
registers dfll or at the end of tegra210_clock resume