Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board

[Icenowy Zheng]

ä 2019å7æ20æ GMT+08:00 äå6:13:18, Maxime Ripard <maxime.ripard@xxxxxxxxxxx> åå:
>On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote:
>> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
>> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI
>Flash.
>> It has a gold finger connector for expansion, and UART is available
>from
>> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or
>> Allwinner V3L SoCs.
>>
>> Add the device tree binding of the basic version of the core board --
>> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@xxxxxxx>
>> ---
>> No changes since v3.
>>
>> Patch introduced in v2.
>>
>>  Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml
>b/Documentation/devicetree/bindings/arm/sunxi.yaml
>> index 000a00d12d6a..48c126a7a848 100644
>> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
>> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
>> @@ -353,6 +353,11 @@ properties:
>>            - const: licheepi,licheepi-zero
>>            - const: allwinner,sun8i-v3s
>>
>> +      - description: Lichee Zero Plus (with S3, without eMMC/SPI
>Flash)
>> +        items:
>> +          - const: sipeed,lichee-zero-plus
>> +          - const: allwinner,sun8i-s3
>
>If the S3 is just a rebranded V3, then we should have the v3 compatile
>in that list too.

S3 is V3 with copackaged DDR3 DRAM.

It's pin incompatible w/ V3.

>
>Maxime
>
>--
>Maxime Ripard, Bootlin
>Embedded Linux and Kernel engineering
>https://bootlin.com

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