Re: [PATCH v1 1/2] genirq: Check for level based percpu irq

[Jiaxun Yang]

17.01.2020, 09:29, "Thomas Gleixner" <tglx@xxxxxxxxxxxxx>:
> Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> writes:
>> ÂMIPS processors implemented their IPI IRQ and CPU interrupt line
>> Âas level triggered IRQ. However, our current percpu_irq flow is trying
>> Âdo it in a level triggered manner.
>

Hi Thomas,

Thanks for your kind explanation.

That appears to be my misunderstanding of the trigger type.

Paul, I have confirmed it seems fine to handle percpu IRQ without mask
it on both Ingenic and Loongson processors. How about other MIPS Cores?
Could you please help check that?

Thanks.

--
Jiaxun Yang