Re: [PATCHv2 1/2] clk: rockchip: rk3588: make gate linked clocks ignore unused

From: zhangqing
Date: Thu Jul 27 2023 - 22:53:05 EST


在 2023/7/14 13:33, Jagan Teki 写道:
Hi Sebastian,

On Fri, 14 Jul 2023 at 01:08, Sebastian Reichel
<sebastian.reichel@xxxxxxxxxxxxx> wrote:
Hello Jagan,

On Thu, Jul 13, 2023 at 08:25:03PM +0530, Jagan Teki wrote:
On Tue, 4 Apr 2023 at 01:03, Sebastian Reichel
<sebastian.reichel@xxxxxxxxxxxxx> wrote:
[...]
+ * Recent Rockchip SoCs have a new hardware block called Native Interface
+ * Unit (NIU), which gates clocks to devices behind them. These effectively
+ * need two parent clocks.
+ *
+ * Downstream enables the linked clock via runtime PM whenever the gate is
+ * enabled. This implementation uses separate clock nodes for each of the
+ * linked gate clocks, which leaks parts of the clock tree into DT.
+ *
+ * The GATE_LINK macro instead takes the second parent via 'linkname', but
+ * ignores the information. Once the clock framework is ready to handle it, the
+ * information should be passed on here. But since these clocks are required to
+ * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
+ * clocks critical until a better solution is available. This will waste some
+ * power, but avoids leaking implementation details into DT or hanging the
+ * system.
*/
Does it mean the clk-link topology in the downstream kernel can be
reused the same as normal clock notation?
Yes.

For example, I'm trying to add HCLK_VO1 directly to VO1 syscon instead
of routing to pclk_vo1_grf(done downstream)
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru HCLK_VO1>;
You need PCLK_VO1 (which is currently not exposed; I somehow missed
it).
Maybe this submission is helpful

The true GATE_LINK callback is implemented.

https://patchwork.kernel.org/project/linux-clk/patch/20230728020810.29732-4-zhangqing@xxxxxxxxxxxxxx/

vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;

When enable pclk_vo1grf,will enable pclk_vo1_root and hclk_vo1.

};

This seems breaking syscon for vo1_grf and observed a bus error
while accessing regmap.
I investigated the issue you are seeing some weeks ago when my
co-workers started to work on HDMI RX and TX. You are probably
just missing this patch:

https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commit/ecc6415344957fa88356cec10f8b75a9da603a7b
In fact, I tried this solution as well, by connecting the PCLK_VO1GRF.

vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = <&cru PCLK_VO1GRF>;
};

But the result seems the same, accessing vo1_grf triggers an abort [1]

[1] https://gist.github.com/openedev/e241da8180341ffbf4dc6a26de7efa31

Thanks,
Jagan.

--
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